Publication (Total Citations: 1206)

Journal:

• B. Zhang, A. Nazemi, A. Garg, N. Kocaman,  M.R.Ahmadi, M. Khanpour, H. Zhang, J. Cao, and A.Momtaz, "A 40nm CMOS 195mW / 55mW Dual-Path Receiver AFE for Multi-standard 8.5-to-11.5 Gb/s Serial Links", IEEE Journal of Solid-State Circuits (JSSC), vol. 50, No. 2, pp. 426-439, Feb. 2015. Citation: 19

• U.Singh, A.Garg, B.Raghavan, N.Huang, H.Zhang , Z.Huang, A.Momtaz, and J.Cao, "A 780mW 4×28Gb/s Transceiver for 100GbE Gearbox PHY in 40nm CMOS", IEEE Journal of Solid-State Circuits (JSSC), vol. 49, No. 12, pp. 3116-3129, Dec. 2014. Citation: 42

• H. Zhang and E. Sánchez-Sinencio, "Linearization Techniques for CMOS Low Noise Amplifiers: A Tutorial", IEEE Transactions on Circuits and Systems, Part I: Regular Papers , vol. 58, No.1, pp. 22-36, Jan. 2011 [Abstract] [PDF]   Citation: 334

• H. Zhang,  "High Performance RF and Baseband Analog-to-Digital Interface for Multi-Standard/Wideband Applications", Ph.D. Thesis  2010

• H. Zhang, X. Fan, and E. Sánchez-Sinencio, "A Low-Power, Linearized, Ultra-Wideband LNA Design Technique", IEEE Journal of Solid-State Circuits (JSSC), vol. 44, No. 2, pp. 320-330, Feb. 2009 [Abstract] [PDF]  Citation: 281

• X. Fan, H. Zhang, and E. Sánchez-Sinencio, "A Noise Reduction and Linearity Improvement Technique for a Differential Cascode LNA", IEEE Journal of Solid-State Circuits (JSSC), vol. 43, No. 3, pp. 588-599, Mar. 2008 [Abstract] [PDF]   Citation: 216

• H. Zhang, Q. Li, and E. Sánchez-Sinencio, "Minimum Current/Area Implementation of Cyclic ADC", IEE Electronics Letters, Vol. 45 Issue 7, pp.351-352, March 2009 [Abstract] [PDF]     Citation: 12

• H. Zhang, Z. Jin and Y. Cui, "Pspice Simulation and Modeling of Infrared Temperature Measure System", Journal of Experimental Technology and Management, vol.21, No.1, pp. 81-85, Jan. 2004

• H. Zhang, "VCSEL Application in LAN—the Development of Low Cost, Fine Quality 1.25Gb/s Laser Transceiver", Series of Selected Papers from Chun–Tsung Scholars, pp. 659-682, 2003

Conference:

• G. Li, A. Garg, T. He, U. Singh, J. Zhang, L. Rao, C. Liu, M. Nazari, Y. Liu, Y. Liu, H. Zhang, T. Ali, H-G. Rhew, J. Ru, D. Cui, A. Nazemi, B. Zhang, A. Momtaz, J. Cao, "A 600Gb/s DP-QAM64 Coherent Optical Transceiver Front-End with 4x105GS/s 8b ADC/DAC in 16nm CMOS", 2024 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, Feb.19-22, 2024



• N. Kocaman, U. Singh, B. Raghavan, A. Iyer, K. Thasari, S. Surana, J. Jung, J. Jeong, H. Zhang, A. Vasani, Y. Shim, Z. Huang, A. Garg, M. Lee, B. Wu, F. Liu, R. Wang, M. Loh, A. Wang, M. Caresosa, B. Zhang, A. Momtaz, "An 182mW 1-60Gbps Configurable PAM4/NRZ Transceiver for High-Density IO’s in 7-nm FinFET Technology", 2022 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, Feb.20-24, 2022
  
  
• D. Cui, J. Cao, A. Nazemi, T. He, G. Li, B. Catli, K. Hu, H. Zhang, B. Rhew, S. Sheng, Y. Shim, B. Zhang, A. Momtaz, "High Speed Data Converters and Their Applications in Optical Communication System", 2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), Miami, FL, Oct.22-25, 2017. Citation: 1
  
  
• J. Cao, D. Cui, A. Nazemi, T. He, G. Li, B. Catli, M. Khanpour, K. Hu, T, Ali, H. Zhang, H. Yu, B. Rhew, S. Sheng, Y. Shim, B. Zhang, A. Momtaz, "Transmitter and Receiver for 100Gbps Coherent Networks with Integrated 4x64GSps 8bit ADCs and DACs in 20nm CMOS", 2017 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, Feb.5-9, 2017. Citation: 40
  
  
• D. Cui, H. Zhang, N. Huang, A. Nazemi, B. Catli, H.G.Rhew, B. Zhang, A.Momtaz, J.Cao, "A 320mW 32Gb/s 8b ADC-Based PAM-4 Analog Front-End with Programmable Gain Control and Analog Peaking in 28nm CMOS", 2016 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, Jan.31-Feb.4, 2016.  Citation: 75
  
  
• S. Lee, D. Tran, T. Ali, B. Çatlı, H. Zhang, W. Zhang, M. Abdul-Latif, Z. Huang, G. Li, M. R. Ahmadi, and A. Momtaz, "A 23mW/lane 1.2-6.8Gb/s Multi-standard Transceiver in 28nm CMOS", 2014 IEEE Asian Solid-State Circuits Conference (ASSCC), Taiwan, November 10-12, 2014. Citation: 1

• U.Singh, A.Garg, B.Raghavan, N.Huang, H.Zhang , Z.Huang, A.Momtaz, and J.Cao, "A 780mW 4×28Gb/s Transceiver for 100GbE Gearbox PHY in 40nm CMOS", 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, February 9-13, 2014; pp.40 - 41. Citation: 3

• H. Zhang, E. Sánchez-Sinencio, "Linearization Techniques for CMOS LNAs: A Tutorial", IEEE 2013 International Microwave Symposium,  WSE-2, Seattle, WA; June 2, 2013 [Abstract]

• B. Zhang, A. Nazemi, A. Garg, N. Kocaman,  M.R.Ahmadi, M. Khanpour, H. Zhang, J. Cao, and A.Momtaz, "A 195mW / 55mW Dual-Path Receiver AFE for Multi-standard 8.5-to-11.5 Gb/s Serial Links in 40nm CMOS", 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, February 17-21, 2013; pp.34 - 35 [Abstract] [PDF]    Citation: 40

• H. Zhang, J. Tan, C. Zhang, H. Chen, and E. Sánchez-Sinencio, "A 0.6-to-200MSPS Speed Reconfigurable and 1.9-to-27mW Power Scalable 10bit ADC", IEEE 2011 European Solid-State Circuits Conference (ESSCIRC), Helsinki, Finland, pp. 367 - 370, September 12-16, 2011 [Abstract] [PDF] Citation: 8

• H. Zhang, M. M. Elsayed, and E. Sánchez-Sinencio, "New Applications and Technology Scaling Driving Next Generation A/D Converters", IEEE European Conference on Circuit Theory and Design(ECCTD), Antalya, Turkey, August 23-27, 2009, pp.109-112  [Abstract] [PDF]   Citation: 9

Patents:

• A. Iyer, H. Zhang, J. Jeong,  B. Zhang, K. Thasari, U. Singh, and N. Kocaman, "High Speed Receiver", United States Patent. US 10749714 B2. Issued Aug.18, 2020.

• H. Zhang, J. Jeong,  B. Zhang, A. Iyer, K. Thasari, U. Singh, and N. Kocaman, "High Speed Receiver", United States Patent. US 10505767 B1. Issued Dec.10, 2019.

• H. Zhang, D. Cui, J. Cao, and  A.Momtaz, "Phase Adjustment Scheme for Time-interleaved ADCs",  United States Patent. US 9065464 B2. Issued Jun.23, 2015. Citation: 4

• H. Zhang, D. Cui,  and J. Cao, "Clock Generator for Use in A Time-interleaved ADC and Methods for Use therewith", United States Patent. US 8902094 B1. Issued Dec.2, 2014. Citation: 16

• H. Zhang, M. Khanpour,  J. Cao, C. Liu, and A.Momtaz, "Transceiver Including a High Latency Communication Channel and a Low Latency Communication Channel", United States Patent. US 8873606 B2. Issued Oct.28, 2014. Citation: 101

• B. Zhang, A. Nazemi, M.R. Ahmadi, A.Momtaz, H. Zhang, and H. Maarefi, "DSP Receiver with High Speed Low BER ADC",  United States Patent. US 8836553 B2. Issued Sep.16, 2014. Citation: 4